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 STW11NK90Z
N-channel 900V - 0.82 - 9.2A - TO-247 Zener-protected SuperMESHTM Power MOSFET
General features
Type STW11NK90Z

VDSS 900V
RDS(on) <0.98
ID 9.2A
Pw 200W
100% avalanche tested Extremely high dv/dt capability Gate charge minimized Very low intrinsic capacitances Very good manufacturing repeability TO-247
Description
The SuperMESHTM series is obtained through an extreme optimization of ST's well established strip-based PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage Power MOSFETs including revolutionary MDmeshTM products
Internal schematic diagram
Applications
Switching application
Order codes
Part number STW11NK90Z Marking W11NK90Z Package TO-247 Packaging Tube
July 2006
Rev 2
1/12
www.st.com 12
Contents
STW11NK90Z
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 5
3 4 5
Test circuits
.............................................. 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STW11NK90Z
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VDGR VGS ID ID IDM
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Drain-gate voltage (RGS = 20K) Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC=100C Drain current (pulsed) Total dissipation at TC = 25C Derating factor Value 900 900 30 9.2 5.8 36.8 200 1.51 6000 4.5 -55 to 150 Unit V V V A A A W W/C V V/ns C
PTOT
VESD(G-D) dv/dt TJ Tstg
(2)
Gate source ESD(HBM-C=100pF, R=1.5K) Peak diode recovery voltage slope Operating junction temperature Storage temperature
1. Pulse width limited by safe operating area 2. ISD < 9.2A, di/dt < 200A/s, VDD =80%V(BR)DSS
Table 2.
Symbol Rthj-case Rthj-a Tl
Thermal resistance
Parameter Thermal resistance junction-case Max Thermal resistance junction-ambient Max Maximum lead temperature for soldering purpose Value 0.66 50 300 Unit C/W C/W C
Table 3.
Symbol IAR EAS
Avalanche data
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj Max) Single pulse avalanche energy (starting Tj=25C, Id=Iar, Vdd=50V) Value 9.2 400 Unit A mJ
3/12
Electrical characteristics
STW11NK90Z
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 1mA, VGS= 0 VDS = Max rating, VDS = Max rating @125C VGS = 20V VDS= VGS, ID = 100A VGS= 10V, ID= 4.6A 3 3.75 0.82 Min. 900 1 50
10
Typ.
Max.
Unit V A A A V
4.5 0.98
Table 5.
Symbol gfs (1) Ciss Coss Crss
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Test conditions VDS =15V, ID = 4.6A Min. Typ. 11 3000 240 48 83 95 14 49 115 Max. Unit S pF pF pF pF nC nC nC
VDS =25V, f=1 MHz, VGS=0
Coss eq(2). Equivalent output capacitance Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge
VGS=0, VDS =0V to 720V VDD=720V, ID = 9.2A VGS =10V (see Figure 14)
1. Pulsed: pulse duration=300s, duty cycle 1.5% 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS inceases from 0 to 80% VDSS
Table 6.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD=450 V, ID= 4.6A, RG=4.7, VGS=10V (see Figure 13) Min. Typ. 30 19 76 50 Max. Unit ns ns ns ns
4/12
STW11NK90Z
Electrical characteristics
Table 7.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD=9.2A, VGS=0 ISD=9.2A, di/dt = 100A/s, VDD=50V, Tj=25C (see Figure 18) ISD=9.2A, di/dt = 100A/s, VDD=50V, Tj=150C (see Figure 18) 584 6 21 Test conditions Min. Typ. Max. 9.2 36.8 1.6 Unit A A V ns C A
Reverse recovery time Reverse recovery charge Reverse recovery current
790 8.7 22
ns C A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300s, duty cycle 1.5%
Table 8.
Symbol BVGSO(1)
1.
Gate-source zener diode
Parameter Gate-source breakdown voltage Test conditions Igs=1mA (open drain) Min. 30 Typ. Max. Unit V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
5/12
Electrical characteristics
STW11NK90Z
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Normalized BVDSS vs temperature
Figure 6.
Static drain-source on resistance
6/12
STW11NK90Z Figure 7. Gate charge vs gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
Figure 12. Maximum avalanche energy vs temperature
7/12
Test circuits
STW11NK90Z
3
Test circuits
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
8/12
STW11NK90Z
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com
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Package mechanical data
STW11NK90Z
TO-247 MECHANICAL DATA
mm. MIN. 4.85 2.20 1.0 2.0 3.0 0.40 19.85 15.45 5.45 14.20 3.70 18.50 3.55 4.50 5.50 3.65 5.50 0.140 0.177 0.216 14.80 4.30 0.560 0.14 0.728 0.143 0.216 TYP MAX. 5.15 2.60 1.40 2.40 3.40 0.80 20.15 15.75 MIN. 0.19 0.086 0.039 0.079 0.118 0.015 0.781 0.608 0.214 0.582 0.17 inch TYP. MAX. 0.20 0.102 0.055 0.094 0.134 0.03 0.793 0.620
DIM. A A1 b b1 b2 c D E e L L1 L2 oP oR S
10/12
STW11NK90Z
Revision history
5
Revision history
Table 9.
Date 30-Mar-2006 25-Jul-2006
Revision history
Revision 1 2 First release Modified value on Avalanche data Changes
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STW11NK90Z
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